Sr. Semiconductor Advanced Packaging Designer (Cadence Allegro)
Company: L3Harris Technologies
Location: Palm Bay
Posted on: October 30, 2024
Job Description:
Job Title: Sr. Semiconductor Advanced Packaging Designer
(Cadence Allegro)Job Code: 16822Job Location: - Palm Bay, FLJob
Schedule: 9/80 (Every other Friday off!)Relocation: Relocation
assistance may be provided for qualified applicants -Job
Description: -This role will require you to design complex die
level component packages requiring knowledge of Silicon substrates,
die stacking, TSVs and die attachment technologies. Designs will be
captured using Cadence EDA tools including Advanced Package
Designer (APD) and System Connectivity manager (SCM). Your primary
responsibilities will require an understanding of advanced
packaging technologies, packaging materials and material properties
along with processes and an intimate knowledge of CAD SW and design
verification tools. This position requires interface with the
fabrication and assembly team with the opportunity to become more
involved in these operations, designing interconnect test
structures to enable chip-to-chip process development. - Essential
Functions: -
- Work closely with a small team to achieve and develop designs
for multi die packages using Cadence APD (Advance Package designer
24.1) and Cadence SCM. Understand and apply design verification
software (PVS, LVS), incorporate design data in a Wafer level
design working with internal and external foundry engineers
coordinating fabrication features such as targets, metallization
plans and process flows.
- Candidate will be responsible for creating and maintaining
schematics (Cadence SCM) and design databases (Cadence APD)
- Must be able to adapt to an evolving process and work closely
with teammates providing up to date changes.
- Position will require individual to interface with other team
members on tool development and process flow; as well as designing
test structures for process development and integration.
- Manages complex interposer designs, works across multiple
industry standard/non-standard die design CAD tools, develops
processes, performs failure analysis investigations, RCCAs, and
leads a team of designers.
- Create design process control documentation and mentor/lead
other personnel on design rules and processes.
- Work with general oversight and lead technical team of up to 6
additional engineers and designers.
- Domestic and International Travel Required up to 25% of
timeQualifications:
- Bachelor's Degree and a minimum of 9 years of prior relevant
experience or Graduate Degree and a minimum of 7 years of prior
related experience. In lieu of a degree, minimum of 13 years of
prior related experience.
- Ability to obtain a Top Secret/SCI U.S. government Security
Clearance
- Experience using Cadence Allegro Package Design suite
- 5+ years experience with updating, operating, and designing
with new semiconductor design CAD tools and processes
- Prior or current experience documenting, communicating, and
presenting technical topics/recommendations/issues/concerns to
internal and external customers
- Experience in advanced microelectronics packaging including
through silicon vias, redistribution layers (RDL), chip stacking,
and fan outPreferred Additional Skills:
- Active Top Secret/SCI clearance -
- Ability to lead a design team, size 2-10 people.
- Experience using Cadence APD (Advance Package designer 24.1)
and Cadence SCM
- Experience with silicon photonics
- Autocad, L-Edit, Klayout, or equivalent 2D mask layout tool
-
Keywords: L3Harris Technologies, Titusville , Sr. Semiconductor Advanced Packaging Designer (Cadence Allegro), Other , Palm Bay, Florida
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